In a memory cell having a two transistors/one capacitor (2T/1C) configuration, the capacitor C stores charges representative of logic “1” or logic “0”, and the first control transistor Q1 and the second control transistor Q2 perform reading operation and writing operation, respectively.
Because 2T/1C memory device stores data in the capacitor, it should be refreshed at a time interval and can only be used as a dynamic random access memory (DRAM). A refresh period of the 2T/1C memory cell should be smaller than a retention time of the capacitor. Due to periodical refresh of the 2T/1C memory cell, the memory has a complex controller circuit and has a large power dissipation.
In the 2T/1C memory cell, it is necessary for the capacitor to have large capacitance so as to provide a retention time as long as possible, which, however, increases occupied area of the memory cell and decreases integration level of the memory.
Thus, it is still desirable to develop a memory cell without a capacitor.